When integrated circuits are manufactured, there is a substantial probability that a particular chip will not function as designed. Because of many manufacturing variabilities, a given chip may not provide the correct outputs for a particular set of inputs. Such faults often occur randomly from one chip to the next, and may occur for any one or more of a great variety of reasons which will be understood by those skilled in the art. Accordingly, standard practice is to subject each chip to a number of test patterns and to measure the output for each one. A fault simulation approach to determine testability is described by Chao et al in U.S. Pat. No. 3,775,598. Fault simulation requires a logical model of the integrated circuit and possible faults are then inserted into the model, corresponding to possible faults in the real chip.
There are various levels of abstraction for the circuit model that can be used in the fault simulation. A general description of simulators of different levels is contained in a technical article entitled "A System Engineer's Guide to Simulators" by Werner et al appearing in VLSI Design, February 1984, pp. 27-31. One type is described by Timoc in U.S. Pat. No. 4,308,616 who adds a fault inserter to physical circuits.
Perhaps the conceptually simplest for CMOS is the switch level. The switch-level representation of a circuit is an interconnection of transistors and the like. Faults are fairly easily inserted into the switch level representation. However, once all the transistors are interconnected according to the design of the chip, the result is a very complex, nonlinear circuit. Such a switch level circuit is difficult to evaluate for the relation of inputs to outputs.
Another type of representation is a Boolean model in which Boolean gates, such as AND or OR gates, are used. A Boolean circuit is much easier to evaluate mathematically. The Boolean model may be more complex than the corresponding switch-level model, but once the model has been set up, sophisticated and efficient computer simulators are available.
Many bipolar circuit elements can be readily converted to Boolean equivalents. However, MOS circuit elements are much more difficult to transform to a Boolean representation with the proper simulation of MOS faults.
One recently developed type of MOS circuits is a differential cascode voltage switch (DCVS). This type of circuit is disclosed by Heller et al in a technical article entitled "Cascode Voltage Switch Logic Family" appearing in Proceedings of IEEE International Solid-State Circuits Conference, Feb. 22-24, 1984, San Francisco, Calif. This type of circuit is also described in patent application, Ser. No. 554,146 filed Nov. 21, 1983 by W. R. Griffin et al.
A method for the "Fault Simulation for Differential Cascode Voltage Switches" is set forth and described in U.S. patent application, Ser. No. 709,612, filed Mar. 8, 1985 and assigned to the same assignee as the present invention. The fault simulation method described in this application has essentially the same objective as the present invention but deals with a different class of circuits. The present invention deals with static CMOS circuits designed from book sets.
With static CMOS circuits there are hazards (or "glitches") and charge sharing effects that introduce problems which are not present in DCVS circuits. It is, however, absolutely necessary for these effects to be considered to achieve an effective circuit model as will be apparent from the subsequent description.
The need for better methods of modeling and simulating is exacerbated in the case of circuit packages where a complete circuit is designed with a large plurality of predesigned individual circuits which perform various logic functions which might include ANDs, ORs, EXCLUSIVE ORs, NANDs, NORs, inverters, multiplexors, etc. These circuits are designed from a large catalog of interconnectable functional elements. Such catalogs are known in the art by various names such as master images, master slices, book sets, gate arrays, standard cells, etc.
In the present application catalogs are referred to as book sets and the individual combinatorial circuits contained thereon are referred to as books.
There is a great need in the industry to provide a means for accurately modeling the overall circuit and, utilizing these models, to develop an accurate simulator which may be used for purposes of testing the design or, as described subsequently, for testing the effectiveness of the diagnostic patterns which are to be utilized for purposes of testing the operability of the chips produced.
CMOS is considered the future technology for a wide variety of products in the electronic industry. An important part of any design system, and in particular a design system for a new CMOS technology, is the support provided for testability analysis.
In the following portions of the specification numerous references are made to additional prior art publications and patents. These are located in the single Bibliography listing at the end of the specification in ascending order by year of publication and may be readily accessed from the reference codes utilized.
The incompleteness of the classical stuck-at fault models for CMOS is now well recognized [GAL80, WAD78]. The fault models proposed for CMOS include transistor stuck nonconducting and stuck conducting faults, as well as shorts and opens in connections, in addition to the classical stuck-at faults described in [ELZ81, CHI83, JAI83]. In static CMOS the generation of test sequences for sequential faults is further complicated by effects of stray delays. This was first introduced in [RED83], where the invalidation of test sequences due to stray delays is analyzed. Some of the concepts that have been developed on hazards which are relevant to the present invention will now be discussed.
A combinational logic network contains a (static) hazard for an input change involving the changing of one or more input variables if and only if (1) the output before the change is equal to the output after the change and (2) during the change a spurious pulse may appear at the output [EIC65].
Consider two input states A and B. The transition subcube T(A,B) is the set of all states that are identical to A and B in the input variables in which A and B agree. T(A,B) is the set of all points (input states) that may be passed through during a transition between A and B. This assumes that the variables change in any order and that variables with constant values do not bounce around [FRI75].
There are two types of hazards: Function hazards and Logic hazards.
A function F is said to have a function hazard for the input change A.fwdarw.B if F(A)=F(B) and there exists some input state C contained in T(A,B) such that F(C).noteq.F(A) [FRI75]. Function hazards are inherent in the function and cannot be removed by implementation changes.
If for the input change A.fwdarw.B there is no function hazard, but a particular realization can produce a spurious pulse during the input change, for some distribution of stray delays (delays in logic elements and in the wiring), the realization is said to contain a logic hazard. This kind of hazard may be removed by modifications to the implementation.
A combinational circuit realizing a function F has a 0-hazard (1-hazard) for transition from input I.sub.1 to I.sub.2 if:
1. F(I.sub.1)=F(I.sub.2)=0 (1), and PA0 2. A 1-pulse (0-pulse) may appear (depending on stray-delay values) during the transition I.sub.1 .fwdarw.I.sub.2.
When modeling hazards in CMOS books the first question that needs to be answered is why it is necessary to be concerned with hazards. Circuit designers are aware of their existence and have designed the logic so that it performs the correct function in their presence. Also, synchronous sequential circuit design techniques have been used in many technologies successfully. The problem is that hazards affect the behavior of defective circuits and, hence, have to be considered. The fault simulator that is used to evaluate coverage of some fault model by a given test set has to model the circuit behavior correctly. In CMOS, a fault can transform a combinational circuit into a sequential one. To detect such faults a sequence of two test patterns is required. The first test pattern is used as a setup by charging or discharging a net in both the faultless and faulty circuits. The presence of a glitch could destroy the setup performed by the first pattern and, thus, invalidate the test sequence [RED83]. (The term `glitch` as used hereinafter, refers to an error condition resulting from a hazard.) The approach taken here is a conservative one: the fault simulator will mark off a fault as being detected by a test set if and only if no combination of stray delays can invalidate the test.
The structure of a CMOS gate is shown in FIG. 1. There is an nFET network and a pFET network connected together to produce the output signal F. A book in a CMOS library may be a CMOS gate or an interconnection of a small number of CMOS gates.
In order to illustrate the effect of hazards, first consider the following scenario: The CMOS gate 2 in FIG. 2 is faulty. To test this fault two patterns P1, P2 are applied to gate 2 in sequence. The change P1.fwdarw.P2 involves only one input variable change to gate 2. However, a hazard in gate 1 could cause a glitch on input k to gate 2 that is supposed to remain constant. This glitch could invalidate the setup performed by pattern P1. The simulator needs to model the behavior of both the faultless and faulty gates correctly with respect to both function and logic hazards.
In the following description of the invention a general method for modeling complex CMOS gates is explained. The general method produces an accurate model which takes into account the static hazards present in the circuit, as well as charge storing nets which can similarly lead to inaccurate models if they are not taken into account.